Turbo Master CPU
| Turbo Master CPU | |
| Device Name: | Turbo Master CPU |
| Manufacturer: | Schnedler Systems |
| Release Price: | $179 US[1], equivalent to about $390 today |
| Released: | 1988[2] |
| Discontinued: | 1992 |
| Processor: | R65C02P4 (65C02 variant) |
| Architecture: | 8-bit |
| Clock Speed: | 4.09 MHz |
| Opcodes: | Documented 6510 opcodes only |
| Support Chips: | |
| RAM: | 64 KBytes SRAM |
| ROM: | |
| Expansion: |
|
| Installation: | External cartridge, connects to expansion port |
| License: | Proprietary |
| Manual: | |
| Info: | |
The Turbo Master CPU was an early CPU accelerator for the Commodore 64 and quite probably the first to have commercial success. It was developed by Steven Carl Schnedler under the company name Schnedler Systems and predated the SuperCPU by several years. It came in two versions, one with JiffyDOS and one without. RUN Magazine featured an in-depth article about the accelerator.
The cartridge connects to the expansion port and contains a CMOS variant of the 6502, the 65C02 (R65C02P4) by Rockwell clocked at 4.09 MHz, effectively quadrupling the C64's processing speed in practice.
Termination of support for the TurboMaster CPU and their other Commodore related products is documented as happening on June 30th, 1992. This notification was posted on the companies Q-Link support thread on that date.
Architecture[edit | edit source]
Unlike the later SuperCPU, which uses a 65816 (a 16-bit processor), the Turbo Master CPU uses the 8-bit 65C02. The 65C02 is backward-compatible with the 6510 and supports all of its documented opcodes, but not the illegal opcodes that some programs use. In the Turbo Master CPU, the C64's internal MOS 6510 is deactivated via a DMA signal while the faster processor on the card takes over. The C64's VIC-II, SID, and CIAs (keyboard and serial bus) continue to be used.
The card features a hardware switch as well as software control to switch between turbo mode (4.09 MHz) and standard speed (1 MHz). This was essential since many C64 programs relied on precise original timing or used undocumented opcodes.
GEOS compatibility and the MasterAdapter[edit | edit source]
Special provision was made to ensure that the accelerator was fully compatible with GEOS, including support for GeoRAM and the REU. To allow the Turbo Master CPU to operate alongside these memory expansions, Schnedler Systems developed the MasterAdapter, a buffered cartridge adapter. The MasterAdapter GEOS driver was developed by Paul Bosacki.
Technical details[edit | edit source]
Construction[edit | edit source]
The Turbo Master CPU's circuit board is a two-layer design containing a total of 19 ICs.[3]
| Component | Type | Function |
|---|---|---|
| IC19 | R65C02P4 (Rockwell) | Main processor, 4.09 MHz |
| IC16, IC17 | 2× 62256 (SRAM, 32K×8) | Total fast working RAM, 64 KBytes |
| IC18 | 27C256 (EPROM, 32K×8) | System ROM including fast loader (JiffyDOS optional) |
| IC1, IC2, IC11 | 74LS244 (3×) | Octal bus buffers for address and data bus |
| IC3, IC4, IC5, IC6, IC8 | 74LS374 (5×) | Octal D-latches for coupling address and data bus |
| IC7 | 74LS688 | 8-bit comparator |
| IC9 | 74LS74 | Dual D-flip-flop for clock generation and synchronization |
| IC10 | 74LS32 | Quad 2-input OR gate |
| IC12 (U4) | PAL16L8 | Address decoder: ROM enable, RAM2 enable, I/O access detection |
| IC13 (U1) | PAL16L8 | Write access detection for $00/$01, RAM1 enable, SO/RDY control, ROM address redirection |
| IC14 | PAL16R4 | PAL (not yet reverse engineered) |
| IC15 | PAL16R6 | PAL (not yet reverse engineered) |
Emulation of the 6510 processor port[edit | edit source]
Unlike the 6510, the 65C02 does not have a processor port at address $01. Since the C64 operating system and many programs control the memory banking bits HIRAM, LORAM, and CHAREN through it, the Turbo Master must reproduce this functionality in its own hardware.
Write accesses to $01 are buffered both into its own SRAM and into IC8.
According to the manual, the processor port $01 is configured as a pure output port: while POKE0,0:POKE1,0 does not cause a crash under BASIC on a standard C64, it will do so with the Turbo Master CPU.
Bit 7 of memory location $00 serves as a software switch for turbo mode: when it is 0, the processor runs at 4.09 MHz.
RAM write accesses[edit | edit source]
Since the VIC-II reads the screen content directly from the C64's internal DRAM, write accesses by the 65C02 must also update the C64 RAM. The Turbo Master CPU has no write cache or write-back buffer — instead, write-through with clock gating is used, and the 65C02 is briefly halted or synchronized with the C64 bus during write accesses.
The Turbo Master CPU cannot access C64 RAM in the range $D000–$DFFF, because the 6510 in the C64 is deactivated and its CPU port outputs cannot be changed. Accordingly, the C64's PLA permanently maps in the I/O registers (and the Color RAM) in the $D000–$DFFF range, not the system RAM. Consequently, the system RAM in that range cannot be accessed via DMA either.
The Turbo Master does emulate the banking signals internally for its own address decoder (U4), but cannot pass them on to the C64 PLA, since LORAM/HIRAM/CHAREN are internal connections between the 6510 and the PLA and are not available via the expansion port.
This affects programs that switch the $D000–$DFFF range to system RAM via banking and store bitmap, text, or character set data there.
The later SuperCPU solved this problem by initializing the 6510 processor port differently at startup and then selecting the appropriate memory configuration via GAME/EXROM on each write access to $Dxxx.
Clock control and bus synchronization[edit | edit source]
The central challenge of the Turbo Master CPU is the coexistence of a processor clocked at 4.09 MHz with the C64's 0.985 MHz bus, which is used by the VIC-II, SID, CIA, and color RAM. This synchronization is handled by IC15, which functions as a clock generator and bus arbiter.
The R65C02P4 has no internal oscillator and is clocked externally. Its PHI0 input (pin 37) is driven by IC15 O1 (pin 14). IC15 in turn is clocked by the C64's DOTCLK (~8 MHz) (CLK input, pin 1). IC15 divides DOTCLK by two, thus generating the 4.09 MHz clock for the 65C02.
IC15 does not only control the clock frequency but can also halt the clock entirely (or synchronize the 65C02 to the C64 bus clock). This occurs in the following cases:
- I/O accesses ($D000–$DFFF)
- VIC-II (badlines/sprite DMA)
- Write accesses to RAM
- External module DMA (e.g., from a REU)
Reception[edit | edit source]
The Turbo Master CPU appeared at a time when the C64 was still widespread, but it was already becoming apparent that the market for hardware expansions would remain limited. As one of the first commercially successful accelerators for the C64, it was a pioneer product that paved the way for (significantly!) later solutions such as the Flash 8 (1994) and the SuperCPU (1996).
Reproductions[edit | edit source]
- Jim Brain (RETRO Innovations) partially analyzed and made available the circuit board and PAL chips of the Turbo Master CPU around 2020.[3]
- Thomas Christoph (COREi64) presented the TurboMaster V3, a modernized reproduction of the Turbo Master CPU, in 2025.[4]
Weblinks[edit | edit source]
- Turbo Master CPU - Owner's Manual (PDF)
- Turbo Master CPU - Git repository with PLD logic, PCB layouts and reference materials
- Additional images (.zip) of the Turbo Master CPU, via archive.org
- Turbo Master: Steven Carl Schnedler's C64 Accelerator Legacy - The Oasis BBS
References[edit | edit source]
- ↑ The Transactor December 1988 (PDF)
- ↑ Owner's Manual: Copyright 1988/89
- ↑ 3.0 3.1 Turbo Master CPU - Git repository with PLD logic, PCB layouts and reference materials
- ↑ Success - TurboMaster Reverse Engineered on Lemon64 and TurboMaster V3 on The Universe of Commodore 64
