turboDisk
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"turboDisk" is the official name of the fast disk access technology used inside the GEOS operating system for Commodore computers. It allowed users of that system to achieve much faster disk access than the stock operating system permitted.
Source[edit | edit source]
Below is the source to the Disk Drive portion of turboDisk that is uploaded and executed inside the various disk drives while turboDisk is in operation. Annotations, and explanations will be added as they become available.
1541 Disk Drive turboDisk[edit | edit source]
M-W at 0400 4c c0 04 4c aa 04 4c 53 05 4c 3b 05 4c 3e 05 4c 49 05 ea ea 60 ea ea 60 ea ea 60 4c 24 05 20 00 05 88 b1 70 aa 4a 4a 4a 4a 85 73 8a 29 0f aa a9 00 8d 00 18 a9 04 2c 00 18 f0 fb 8e 00 18 ea ea 8a 0a 29 0f 8d 00 18 48 68 a5 73 8d 00 18 ea ea ea 0a 29 0f 8d 00 18 98 d0 c7 20 69 04 a2 02 8e 00 18 a9 04 2c 00 18 f0 fb 60 a0 00 20 00 05 88 a9 04 2c 00 18 f0 fb ea ea 24 70 ad 00 18 0a ea 24 70 0d 00 18 ea 0a 0a 0a 0a 85 74 ad 00 18 0a 24 70 48 68 0d 00 18 29 0f 05 74 91 70 98 d0 cf a9 04 2c 00 18 f0 fb 4c fa 04 20 00 05 68 68 a0 00 84 33 a9 ec 8d 0c 1c 20 1b 05 68 85 49 58 60 78 a5 49 48 a0 00 88 d0 fd 20 09 05 f0 fb 20 fa 04 20 09 05 f0 07 20 1b 05 58 20 f4 04 78 a9 05 85 71 a9 10 85 70 a0 04 20 6c 04 20 14 05 20 0f 05 4c d1 04 20 09 05 d0 fb 60 a9 02 8d 00 18 60 20 f4 04 a9 00 8d 00 18 60 a9 04 2c 00 18 60 4c 00 10 00 00 ad 00 1c 09 08 d0 05 a9 f7 2d 00 1c 8d 00 1c 60 a5 1c f0 09 a9 00 85 22 20 8c 06 f0 05 a9 00 85 1c 2c a9 03 4c 4b 05 a9 00 2c a9 02 48 20 e3 06 68 a8 20 fd 06 a5 00 8d 00 03 a0 01 4c fd 06 20 f4 06 20 6a 04 20 5f 05 4c 49 05 ad 00 1c 29 10 d0 05 a9 08 85 00 60 20 c6 05 b0 fa a9 10 20 3c 06 20 e9 f5 85 3a 20 8f f7 ba 86 49 20 10 f5 a2 08 50 fe b8 ca 10 fa 8e 03 1c a9 ce 8d 0c 1c 8a a2 05 8d 01 1c b8 50 fe b8 ca d0 fa a0 bb b9 00 01 50 fe b8 8d 01 1c c8 d0 f4 b1 30 50 fe b8 8d 01 1c c8 d0 f5 50 fe a9 ee 8d 0c 1c 8c 03 1c 84 50 60 20 8c 06 f0 20 a5 22 38 ed 12 05 f0 15 a2 ff b0 06 49 ff 69 01 a2 01 20 f2 05 ad 12 05 85 22 20 ce 06 a9 01 2c a9 03 85 00 c9 02 60 0a a8 86 4a ad 00 1c 29 fe 85 70 a9 1e 85 71 a5 70 18 65 4a 45 70 29 03 45 70 85 70 8d 00 1c a5 71 20 33 06 a5 71 c0 05 90 08 c9 11 90 0a e9 02 d0 06 c9 1c b0 02 69 04 85 71 88 d0 d2 84 4a a9 4b 8d 05 18 ad 05 18 d0 fb 60 85 45 a9 ee 8d 0c 1c a9 05 85 33 a9 12 85 32 a9 03 85 31 a9 00 85 30 a2 01 86 00 ca 8e ab 02 8e fe 02 86 3f 60 a0 00 84 3e 84 3d 88 84 48 ad 00 1c 09 04 8d 00 1c a9 20 24 20 85 20 d0 e6 a2 01 8a 20 f2 05 a2 ff a9 01 20 f2 05 a9 ff 4c 33 06 20 61 06 a5 1c d0 09 a4 00 88 d0 04 a5 22 d0 31 20 7a 06 a9 04 85 70 a9 30 20 3c 06 ba ca ca 86 49 20 b1 f3 a5 18 85 22 a4 00 88 f0 0c c6 70 30 0c a6 70 20 d3 06 38 b0 de 84 1c a8 60 a9 00 85 22 60 20 4b f2 85 43 ad 00 1c 29 9f 1d df 06 8d 00 1c 60 00 20 40 60 20 c6 05 b0 0b a9 00 20 3c 06 ba 86 49 20 d1 f4 60 a9 03 85 71 a9 00 85 70 60 20 f4 06 4c 1e 04 a5 70 18 65 4a 45 70 29 03 45 70 85 70 8d 00 1c a5 71 20 4e 06 a5 71 c0 05 90 08 c9 11 M-E at 0400, CRC 266b * = 0400 ; Program starts at memory location $0400 ; Jump table for main routines 0400 4C C0 04 JMP $04C0 ; Jump to main initialization routine 0403 4C AA 04 JMP $04AA ; Jump to loader exit routine 0406 4C 53 05 JMP $0553 ; Jump to load file routine 0409 4C 3B 05 JMP $053B ; Jump to send command routine 040C 4C 3E 05 JMP $053E ; Jump to execute command routine 040F 4C 49 05 JMP $0549 ; Jump to status return routine ; Small utility routines - probably placeholders or dummy routines 0412 EA NOP ; No operation 0413 EA NOP ; No operation 0414 60 RTS ; Return from subroutine 0415 EA NOP ; No operation 0416 EA NOP ; No operation 0417 60 RTS ; Return from subroutine 0418 EA NOP ; No operation 0419 EA NOP ; No operation 041A 60 RTS ; Return from subroutine 041B 4C 24 05 JMP $0524 ; Jump to disk error handling routine ; Data transmission routine - sends data to the computer 041E 20 00 05 JSR $0500 ; Wait for interface to be ready 0421 88 DEY ; Decrement Y counter 0422 B1 70 LDA ($70),Y ; Load byte from memory pointer at $70 0424 AA TAX ; Transfer accumulator to X 0425 4A LSR A ; Shift right (divide by 2) 0426 4A LSR A ; Shift right (divide by 4) 0427 4A LSR A ; Shift right (divide by 8) 0428 4A LSR A ; Shift right (divide by 16) - get high nibble 0429 85 73 STA $73 ; Store high nibble in $73 042B 8A TXA ; Get original byte back 042C 29 0F AND #$0F ; Mask out high nibble - keep low nibble 042E AA TAX ; Store low nibble in X 042F A9 00 LDA #$00 ; Clear handshake signal 0431 8D 00 18 STA $1800 ; Store to I/O port for serial communication 0434 A9 04 LDA #$04 ; Check for ready signal 0436 2C 00 18 BIT $1800 ; Test bits with I/O port 0439 F0 FB BEQ $0436 ; Loop until ready ; Send low nibble first 043B 8E 00 18 STX $1800 ; Send low nibble to I/O port 043E EA NOP ; Timing delay 043F EA NOP ; Timing delay 0440 8A TXA ; Get low nibble back 0441 0A ASL A ; Shift left 0442 29 0F AND #$0F ; Mask to keep shifted nibble 0444 8D 00 18 STA $1800 ; Send to I/O port 0447 48 PHA ; Push to stack (timing delay) 0448 68 PLA ; Pull from stack (timing delay) ; Send high nibble 0449 A5 73 LDA $73 ; Get high nibble 044B 8D 00 18 STA $1800 ; Send to I/O port 044E EA NOP ; Timing delay 044F EA NOP ; Timing delay 0450 EA NOP ; Timing delay 0451 0A ASL A ; Shift left 0452 29 0F AND #$0F ; Mask high bits 0454 8D 00 18 STA $1800 ; Send to I/O port 0457 98 TYA ; Check if we're done 0458 D0 C7 BNE $0421 ; If Y is not zero, continue with next byte ; Finalize transmission 045A 20 69 04 JSR $0469 ; Call return from subroutine 045D A2 02 LDX #$02 ; Set signal value 045F 8E 00 18 STX $1800 ; Send to I/O port 0462 A9 04 LDA #$04 ; Ready check value 0464 2C 00 18 BIT $1800 ; Test I/O port 0467 F0 FB BEQ $0464 ; Loop until ready 0469 60 RTS ; Return from subroutine ; Data receiving routine - reads data from the computer 046A A0 00 LDY #$00 ; Initialize Y counter to 0 046C 20 00 05 JSR $0500 ; Wait for interface to be ready 046F 88 DEY ; Decrement Y (wraps to 255 on first pass) 0470 A9 04 LDA #$04 ; Ready check value 0472 2C 00 18 BIT $1800 ; Test I/O port 0475 F0 FB BEQ $0472 ; Loop until ready 0477 EA NOP ; Timing delay 0478 EA NOP ; Timing delay ; Read first nibble 0479 24 70 BIT $70 ; Memory timing delay 047B AD 00 18 LDA $1800 ; Read from I/O port 047E 0A ASL A ; Shift left 047F EA NOP ; Timing delay 0480 24 70 BIT $70 ; Memory timing delay 0482 0D 00 18 ORA $1800 ; Combine with next read 0485 EA NOP ; Timing delay 0486 0A ASL A ; Shift left 0487 0A ASL A ; Shift left 0488 0A ASL A ; Shift left 0489 0A ASL A ; Shift left to position high nibble 048A 85 74 STA $74 ; Store in temporary location ; Read second nibble 048C AD 00 18 LDA $1800 ; Read from I/O port 048F 0A ASL A ; Shift left 0490 24 70 BIT $70 ; Memory timing delay 0492 48 PHA ; Push to stack (timing delay) 0493 68 PLA ; Pull from stack (timing delay) 0494 0D 00 18 ORA $1800 ; Combine with next read 0497 29 0F AND #$0F ; Mask to keep low nibble 0499 05 74 ORA $74 ; Combine with high nibble 049B 91 70 STA ($70),Y ; Store complete byte at memory location 049D 98 TYA ; Check if we're done 049E D0 CF BNE $046F ; If Y is not zero, continue with next byte ; Finalize receive 04A0 A9 04 LDA #$04 ; Ready check value 04A2 2C 00 18 BIT $1800 ; Test I/O port 04A5 F0 FB BEQ $04A2 ; Loop until ready 04A7 4C FA 04 JMP $04FA ; Jump to signal completion ; Exit routine 04AA 20 00 05 JSR $0500 ; Wait for interface to be ready 04AD 68 PLA ; Pull return address (discard) 04AE 68 PLA ; Pull return address (discard) 04AF A0 00 LDY #$00 ; Clear Y 04B1 84 33 STY $33 ; Clear memory location $33 04B3 A9 EC LDA #$EC ; Set control register value 04B5 8D 0C 1C STA $1C0C ; Store to VIA control register 04B8 20 1B 05 JSR $051B ; Restore I/O port state 04BB 68 PLA ; Pull processor status 04BC 85 49 STA $49 ; Store to memory 04BE 58 CLI ; Clear interrupt flag 04BF 60 RTS ; Return from subroutine ; Main initialization routine 04C0 78 SEI ; Set interrupt flag (disable interrupts) 04C1 A5 49 LDA $49 ; Get processor status 04C3 48 PHA ; Push to stack 04C4 A0 00 LDY #$00 ; Clear Y 04C6 88 DEY ; Decrement Y (wraps to 255) 04C7 D0 FD BNE $04C6 ; Delay loop ; Check for drive readiness 04C9 20 09 05 JSR $0509 ; Check interface status 04CC F0 FB BEQ $04C9 ; Loop until ready 04CE 20 FA 04 JSR $04FA ; Initialize signal 04D1 20 09 05 JSR $0509 ; Check interface status 04D4 F0 07 BEQ $04DD ; Branch if not ready ; Interface is ready - initialize 04D6 20 1B 05 JSR $051B ; Restore I/O port state 04D9 58 CLI ; Clear interrupt flag 04DA 20 F4 04 JSR $04F4 ; Wait for interface to be busy 04DD 78 SEI ; Set interrupt flag ; Setup memory pointer and read initial data 04DE A9 05 LDA #$05 ; Set high byte of memory pointer 04E0 85 71 STA $71 ; Store to pointer high byte 04E2 A9 10 LDA #$10 ; Set low byte of memory pointer 04E4 85 70 STA $70 ; Store to pointer low byte 04E6 A0 04 LDY #$04 ; Set data length 04E8 20 6C 04 JSR $046C ; Read data from computer ; Jump to loaded code 04EB 20 14 05 JSR $0514 ; Set I/O port state 04EE 20 0F 05 JSR $050F ; Jump to loaded code at $1000 04F1 4C D1 04 JMP $04D1 ; Jump back to check interface ; Interface status routines 04F4 20 09 05 JSR $0509 ; Check interface status 04F7 D0 FB BNE $04F4 ; Loop until busy 04F9 60 RTS ; Return from subroutine ; Signal routines 04FA A9 02 LDA #$02 ; Signal value 04FC 8D 00 18 STA $1800 ; Send to I/O port 04FF 60 RTS ; Return from subroutine ; Wait for interface to be ready 0500 20 F4 04 JSR $04F4 ; Wait for interface to be busy 0503 A9 00 LDA #$00 ; Clear signal 0505 8D 00 18 STA $1800 ; Send to I/O port 0508 60 RTS ; Return from subroutine ; Check interface status 0509 A9 04 LDA #$04 ; Status check value 050B 2C 00 18 BIT $1800 ; Test I/O port 050E 60 RTS ; Return from subroutine ; Jump to loaded code 050F 4C 00 10 JMP $1000 ; Jump to code at $1000 0512 00 BRK ; Break (this appears to be data, not code) 0513 00 BRK ; Break (this appears to be data, not code) ; I/O port control routines 0514 AD 00 1C LDA $1C00 ; Read VIA port B 0517 09 08 ORA #$08 ; Set bit 3 0519 D0 05 BNE $0520 ; Always branch 051B A9 F7 LDA #$F7 ; Bit pattern: 11110111 051D 2D 00 1C AND $1C00 ; Clear bit 3 of VIA port B 0520 8D 00 1C STA $1C00 ; Store to VIA port B 0523 60 RTS ; Return from subroutine ; Disk error handling 0524 A5 1C LDA $1C ; Check error flag 0526 F0 09 BEQ $0531 ; If zero, no error 0528 A9 00 LDA #$00 ; Clear A 052A 85 22 STA $22 ; Store to memory 052C 20 8C 06 JSR $068C ; Call disk status routine 052F F0 05 BEQ $0536 ; Branch if status ok 0531 A9 00 LDA #$00 ; Clear A 0533 85 1C STA $1C ; Clear error flag 0535 2C A9 03 BIT $03A9 ; Test memory location (but appears to be data) 0538 4C 4B 05 JMP $054B ; Jump to status return ; Command routines 053B A9 00 LDA #$00 ; Clear A 053D 2C A9 02 BIT $02A9 ; Test memory location (but appears to be data) 0540 48 PHA ; Push to stack 0541 20 E3 06 JSR $06E3 ; Call disk command routine 0544 68 PLA ; Pull from stack 0545 A8 TAY ; Transfer to Y 0546 20 FD 06 JSR $06FD ; Call data transmission routine 0549 A5 00 LDA $00 ; Get status 054B 8D 00 03 STA $0300 ; Store to status location 054E A0 01 LDY #$01 ; Set Y to 1 0550 4C FD 06 JMP $06FD ; Jump to data transmission routine ; Load file routine 0553 20 F4 06 JSR $06F4 ; Initialize memory pointer 0556 20 6A 04 JSR $046A ; Receive data from computer 0559 20 5F 05 JSR $055F ; Check disk status 055C 4C 49 05 JMP $0549 ; Jump to status return ; Disk status check 055F AD 00 1C LDA $1C00 ; Read VIA port B 0562 29 10 AND #$10 ; Test bit 4 (disk ready) 0564 D0 05 BNE $056B ; Branch if ready 0566 A9 08 LDA #$08 ; Error code for not ready 0568 85 00 STA $00 ; Store to status 056A 60 RTS ; Return from subroutine ; Disk access routines - the rest of the code handles ; various disk operations, drive control, and data transfer 056B 20 C6 05 JSR $05C6 ; Call disk status check 056E B0 FA BCS $056A ; Branch if error 0570 A9 10 LDA #$10 ; Control code 0572 20 3C 06 JSR $063C ; Call disk control routine ; The remaining code handles disk operations, buffer management, ; and the fast transfer protocol that makes this a "turbo" disk routine ; Initialize disk operations 0575 20 E9 F5 JSR $F5E9 ; Call Kernal routine to initialize 0578 85 3A STA $3A ; Store result in zero page 057A 20 8F F7 JSR $F78F ; Call Kernal routine for buffer setup 057D BA TSX ; Transfer stack pointer to X 057E 86 49 STX $49 ; Save stack pointer 0580 20 10 F5 JSR $F510 ; Initialize drive timing ; Timing setup for drive operation 0583 A2 08 LDX #$08 ; Set counter to 8 0585 50 FE BVC $0585 ; Wait for overflow clear (active loop) 0587 B8 CLV ; Clear overflow flag 0588 CA DEX ; Decrement counter 0589 10 FA BPL $0585 ; Loop until counter < 0 ; Set up VIA timers and control registers 058B 8E 03 1C STX $1C03 ; Store X to VIA timer control 058E A9 CE LDA #$CE ; Control register value 0590 8D 0C 1C STA $1C0C ; Set VIA control register 0593 8A TXA ; Get X value 0594 A2 05 LDX #$05 ; Set delay counter ; Timing loop for drive synchronization 0596 8D 01 1C STA $1C01 ; Write to VIA port A 0599 B8 CLV ; Clear overflow flag 059A 50 FE BVC $059A ; Wait for overflow clear 059C B8 CLV ; Clear overflow flag again 059D CA DEX ; Decrement counter 059E D0 FA BNE $059A ; Loop until counter = 0 ; Fast data transfer loop - copy data to/from drive memory 05A0 A0 BB LDY #$BB ; Start with offset $BB 05A2 B9 00 01 LDA $0100,Y ; Get byte from page 1 buffer 05A5 50 FE BVC $05A5 ; Wait for overflow clear 05A7 B8 CLV ; Clear overflow flag 05A8 8D 01 1C STA $1C01 ; Write to VIA port A 05AB C8 INY ; Increment index 05AC D0 F4 BNE $05A2 ; Loop until Y wraps (256 bytes) ; Second transfer loop (different memory source) 05AE B1 30 LDA ($30),Y ; Get byte from memory pointer 05B0 50 FE BVC $05B0 ; Wait for overflow clear 05B2 B8 CLV ; Clear overflow flag 05B3 8D 01 1C STA $1C01 ; Write to VIA port A 05B6 C8 INY ; Increment index 05B7 D0 F5 BNE $05AE ; Loop until Y wraps (256 bytes) ; Finalize transfer 05B9 50 FE BVC $05B9 ; Wait for overflow clear 05BB A9 EE LDA #$EE ; End of transfer value 05BD 8D 0C 1C STA $1C0C ; Store to VIA control register 05C0 8C 03 1C STY $1C03 ; Reset timer 05C3 84 50 STY $50 ; Store Y for later use 05C5 60 RTS ; Return from subroutine ; Disk status check routine 05C6 20 8C 06 JSR $068C ; Check disk controller status 05C9 F0 20 BEQ $05EB ; Branch if no error 05CB A5 22 LDA $22 ; Get previous status 05CD 38 SEC ; Set carry flag for subtraction 05CE ED 12 05 SBC $0512 ; Subtract current status 05D1 F0 15 BEQ $05E8 ; Branch if same as before ; Track adjustment calculation 05D3 A2 FF LDX #$FF ; Set direction negative 05D5 B0 06 BCS $05DD ; Branch if positive difference 05D7 49 FF EOR #$FF ; Complement A 05D9 69 01 ADC #$01 ; Add 1 (two's complement) 05DB A2 01 LDX #$01 ; Set direction positive 05DD 20 F2 05 JSR $05F2 ; Call track adjustment routine 05E0 AD 12 05 LDA $0512 ; Get current status 05E3 85 22 STA $22 ; Update status 05E5 20 CE 06 JSR $06CE ; Update disk controller 05E8 A9 01 LDA #$01 ; Success code 05EA 2C A9 03 BIT $03A9 ; Test memory (no effect, likely data) 05ED 85 00 STA $00 ; Set status 05EF C9 02 CMP #$02 ; Compare with 2 05F1 60 RTS ; Return from subroutine ; Track stepping routine - moves the disk head 05F2 0A ASL A ; Multiply by 2 05F3 A8 TAY ; Transfer to Y as counter 05F4 86 4A STX $4A ; Store direction 05F6 AD 00 1C LDA $1C00 ; Get VIA port B 05F9 29 FE AND #$FE ; Clear bit 0 05FB 85 70 STA $70 ; Store temporarily 05FD A9 1E LDA #$1E ; Constant for timing 05FF 85 71 STA $71 ; Store in memory ; Stepper motor control loop 0601 A5 70 LDA $70 ; Get current value 0603 18 CLC ; Clear carry 0604 65 4A ADC $4A ; Add direction 0606 45 70 EOR $70 ; XOR with previous 0608 29 03 AND #$03 ; Mask bits 0-1 060A 45 70 EOR $70 ; XOR back 060C 85 70 STA $70 ; Store result 060E 8D 00 1C STA $1C00 ; Write to stepper control 0611 A5 71 LDA $71 ; Get timing constant 0613 20 33 06 JSR $0633 ; Delay routine ; Adjust stepper timing based on track position 0616 A5 71 LDA $71 ; Get timing value 0618 C0 05 CPY #$05 ; Compare with 5 061A 90 08 BCC $0624 ; Branch if less 061C C9 11 CMP #$11 ; Compare with $11 061E 90 0A BCC $062A ; Branch if less 0620 E9 02 SBC #$02 ; Subtract 2 0622 D0 06 BNE $062A ; Branch if not zero 0624 C9 1C CMP #$1C ; Compare with $1C 0626 B0 02 BCS $062A ; Branch if greater or equal 0628 69 04 ADC #$04 ; Add 4 062A 85 71 STA $71 ; Store updated timing 062C 88 DEY ; Decrement counter 062D D0 D2 BNE $0601 ; Loop until counter reaches zero 062F 84 4A STY $4A ; Reset direction 0631 A9 4B LDA #$4B ; Constant for final timing ; Delay subroutine using VIA timer 0633 8D 05 18 STA $1805 ; Set timer value 0636 AD 05 18 LDA $1805 ; Read timer 0639 D0 FB BNE $0636 ; Loop until timer expires 063B 60 RTS ; Return from subroutine ; Disk controller command routine 063C 85 45 STA $45 ; Store command code 063E A9 EE LDA #$EE ; VIA control value 0640 8D 0C 1C STA $1C0C ; Set VIA control register 0643 A9 05 LDA #$05 ; High byte memory address 0645 85 33 STA $33 ; Set memory pointer high 0647 A9 12 LDA #$12 ; Low byte memory address 0649 85 32 STA $32 ; Set memory pointer low 064B A9 03 LDA #$03 ; Buffer number 064D 85 31 STA $31 ; Set buffer number 064F A9 00 LDA #$00 ; Zero value 0651 85 30 STA $30 ; Clear work area 0653 A2 01 LDX #$01 ; Set status value 0655 86 00 STX $00 ; Store status 0657 CA DEX ; X = 0 0658 8E AB 02 STX $02AB ; Clear memory location 065B 8E FE 02 STX $02FE ; Clear another location 065E 86 3F STX $3F ; Clear work register 0660 60 RTS ; Return from subroutine ; Controller initialization routine 0661 A0 00 LDY #$00 ; Y = 0 0663 84 3E STY $3E ; Clear work register 0665 84 3D STY $3D ; Clear another register 0667 88 DEY ; Y = 255 0668 84 48 STY $48 ; Set register for maximum value 066A AD 00 1C LDA $1C00 ; Get VIA port B 066D 09 04 ORA #$04 ; Set bit 2 066F 8D 00 1C STA $1C00 ; Update VIA port B 0672 A9 20 LDA #$20 ; Test value 0674 24 20 BIT $20 ; Test with memory 0676 85 20 STA $20 ; Store back to memory 0678 D0 E6 BNE $0660 ; Branch if not zero (always) ; Disk head calibration routine 067A A2 01 LDX #$01 ; Forward direction 067C 8A TXA ; A = 1 067D 20 F2 05 JSR $05F2 ; Step track forward 0680 A2 FF LDX #$FF ; Backward direction 0682 A9 01 LDA #$01 ; Step size 0684 20 F2 05 JSR $05F2 ; Step track backward 0687 A9 FF LDA #$FF ; Maximum delay 0689 4C 33 06 JMP $0633 ; Jump to delay routine ; Disk controller status check 068C 20 61 06 JSR $0661 ; Initialize controller 068F A5 1C LDA $1C ; Get error flag 0691 D0 09 BNE $069C ; Branch if error 0693 A4 00 LDY $00 ; Get status 0695 88 DEY ; Decrement 0696 D0 04 BNE $069C ; Branch if not zero 0698 A5 22 LDA $22 ; Get track position 069A D0 31 BNE $06CD ; Branch if not zero ; Reset controller and handle errors 069C 20 7A 06 JSR $067A ; Calibrate head 069F A9 04 LDA #$04 ; Retry count 06A1 85 70 STA $70 ; Store retry counter 06A3 A9 30 LDA #$30 ; Controller command 06A5 20 3C 06 JSR $063C ; Execute command 06A8 BA TSX ; Get stack pointer 06A9 CA DEX ; Decrement 06AA CA DEX ; Decrement again 06AB 86 49 STX $49 ; Save stack pointer ; Call disk routines in ROM 06AD 20 B1 F3 JSR $F3B1 ; Call ROM disk routine 06B0 A5 18 LDA $18 ; Get current track 06B2 85 22 STA $22 ; Store current track 06B4 A4 00 LDY $00 ; Get status 06B6 88 DEY ; Decrement 06B7 F0 0C BEQ $06C5 ; Branch if zero (good status) 06B9 C6 70 DEC $70 ; Decrement retry counter 06BB 30 0C BMI $06C9 ; Branch if negative (out of retries) 06BD A6 70 LDX $70 ; Get retry counter 06BF 20 D3 06 JSR $06D3 ; Call retry routine 06C2 38 SEC ; Set carry flag 06C3 B0 DE BCS $06A3 ; Always branch to retry ; Successful operation 06C5 84 1C STY $1C ; Clear error flag 06C7 A8 TAY ; Transfer A to Y 06C8 60 RTS ; Return from subroutine ; Failed operation 06C9 A9 00 LDA #$00 ; Zero value 06CB 85 22 STA $22 ; Clear track position 06CD 60 RTS ; Return from subroutine ; Update disk controller 06CE 20 4B F2 JSR $F24B ; Call ROM drive routine 06D1 85 43 STA $43 ; Store result 06D3 AD 00 1C LDA $1C00 ; Get VIA port B 06D6 29 9F AND #$9F ; Clear bits 5-6 06D8 1D DF 06 ORA $06DF,X ; OR with table value indexed by X 06DB 8D 00 1C STA $1C00 ; Update VIA port B 06DE 60 RTS ; Return from subroutine ; Motor control table 06DF 00 BRK ; Value 0 (motor off) 06E0 20 40 60 JSR $6040 ; Values for different motor states (data, not code) ; Execute disk command 06E3 20 C6 05 JSR $05C6 ; Check disk status 06E6 B0 0B BCS $06F3 ; Branch if error 06E8 A9 00 LDA #$00 ; Command code 06EA 20 3C 06 JSR $063C ; Execute command 06ED BA TSX ; Get stack pointer 06EE 86 49 STX $49 ; Save stack pointer 06F0 20 D1 F4 JSR $F4D1 ; Call ROM disk routine 06F3 60 RTS ; Return from subroutine ; Initialize memory pointer for file operations 06F4 A9 03 LDA #$03 ; High byte 06F6 85 71 STA $71 ; Set pointer high byte 06F8 A9 00 LDA #$00 ; Low byte 06FA 85 70 STA $70 ; Set pointer low byte 06FC 60 RTS ; Return from subroutine ; File data transmission routine 06FD 20 F4 06 JSR $06F4 ; Initialize pointer 0700 4C 1E 04 JMP $041E ; Jump to transmission routine ; Alternative stepper motor control routine 0703 A5 70 LDA $70 ; Get current value 0705 18 CLC ; Clear carry 0706 65 4A ADC $4A ; Add direction 0708 45 70 EOR $70 ; XOR with previous 070A 29 03 AND #$03 ; Mask bits 0-1 070C 45 70 EOR $70 ; XOR back 070E 85 70 STA $70 ; Store result 0710 8D 00 1C STA $1C00 ; Write to stepper control 0713 A5 71 LDA $71 ; Get timing value 0715 20 4E 06 JSR $064E ; Alternative timing routine 0718 A5 71 LDA $71 ; Get timing again 071A C0 05 CPY #$05 ; Compare Y with 5 071C 90 08 BCC $0726 ; Branch if less than 5 071E C9 11 CMP #$11 ; Compare with $11 0720 .END ; End of code
1571 Disk Drive turboDisk[edit | edit source]
M-W at 0400
4c c4 04 4c aa 04 4c 65 05 4c 4d 05 4c 50 05 4c 5b 05 ea ea 60 ea ea 60 ea ea 60 4c 35 05 20 11
05 88 b1 70 aa 4a 4a 4a 4a 85 73 8a 29 0f aa a9 00 8d 00 18 a9 04 2c 00 18 f0 fb 8e 00 18 ea ea
8a 0a 29 0f 8d 00 18 48 68 a5 73 8d 00 18 ea ea ea 0a 29 0f 8d 00 18 98 d0 c7 20 69 04 a2 02 8e
00 18 a9 04 2c 00 18 f0 fb 60 a0 00 20 11 05 88 a9 04 2c 00 18 f0 fb ea ea 24 70 ad 00 18 0a ea
24 70 0d 00 18 ea 0a 0a 0a 0a 85 74 ad 00 18 0a 24 70 48 68 0d 00 18 29 0f 05 74 91 70 98 d0 cf
a9 04 2c 00 18 f0 fb 4c 0b 05 20 11 05 68 68 a0 00 84 33 a9 ec 8d 0c 1c 20 2c 05 68 85 49 38 66
3b 4c 4e 90 ad 0f 18 29 20 f0 06 38 66 3b 20 32 90 78 a5 49 48 a0 00 88 d0 fd 20 1a 05 f0 fb 20
0b 05 20 1a 05 f0 07 20 2c 05 58 20 05 05 78 a9 05 85 71 a9 21 85 70 a0 04 20 6c 04 20 25 05 20
20 05 4c e2 04 20 1a 05 d0 fb 60 a9 02 8d 00 18 60 20 05 05 a9 00 8d 00 18 60 a9 04 2c 00 18 60
4c 00 10 00 00 ad 00 1c 09 08 d0 05 a9 f7 2d 00 1c 8d 00 1c 60 a9 00 85 22 20 2a 07 a5 00 c9 02
b0 06 ad 03 03 29 80 2c a9 03 4c 5d 05 a9 00 2c a9 02 48 20 2a 07 68 a8 20 44 07 a5 00 8d 00 03
a0 01 4c 44 07 20 3b 07 20 6a 04 20 71 05 4c 5b 05 ad 00 1c 29 10 d0 05 a9 08 85 00 60 20 d8 05
b0 fa a9 10 20 57 06 20 e9 f5 85 3a 20 8f f7 ba 86 49 20 10 f5 a2 08 50 fe b8 ca 10 fa 8e 03 1c
a9 ce 8d 0c 1c 8a a2 05 8d 01 1c b8 50 fe b8 ca d0 fa a0 bb b9 00 01 50 fe b8 8d 01 1c c8 d0 f4
b1 30 50 fe b8 8d 01 1c c8 d0 f5 50 fe a9 ee 8d 0c 1c 8c 03 1c 84 50 60 20 cf 06 f0 29 20 a7 06
a5 22 38 ed 23 05 f0 1b a2 ff b0 06 49 ff 69 01 a2 01 20 0d 06 ad 23 05 85 22 c9 24 90 02 e9 23
20 15 07 a9 01 2c a9 03 85 00 c9 02 60 0a a8 86 4a ad 00 1c 29 fe 85 70 a9 1e 85 71 a5 70 18 65
4a 45 70 29 03 45 70 85 70 8d 00 1c a5 71 20 4e 06 a5 71 c0 05 90 08 c9 11 90 0a e9 02 d0 06 c9
1c b0 02 69 04 85 71 88 d0 d2 84 4a a9 4b 8d 05 18 ad 05 18 d0 fb 60 85 45 a9 ee 8d 0c 1c a9 05
85 33 a9 23 85 32 a9 03 85 31 a9 00 85 30 a2 01 86 00 ca 8e ab 02 8e fe 02 86 3f 60 a0 00 84 3e
84 3d 88 84 48 ad 00 1c 09 04 8d 00 1c a9 20 24 20 85 20 d0 e6 a2 01 8a 20 0d 06 a2 ff a9 01 20
0d 06 a9 ff 4c 4e 06 ad 23 05 c9 24 a5 22 b0 09 c9 24 90 0e e9 23 18 90 07 c9 24 b0 03 69 23 38
85 22 ad 0f 18 29 fb 90 02 09 84 8d 0f 18 60 20 7c 06 a5 1c d0 09 a4 00 88 d0 04 a5 22 d0 35 18
20 c2 06 20 95 06 a9 04 85 70 a9 30 20 57 06 ba ca ca 86 49 20 b1 f3 a5 18 85 22 a4 00 88 f0 0c
c6 70 30 0c a6 70 20 1a 07 38 b0 de 84 1c a8 60 a9 00 85 22 60 20 4b f2 85 43 ad 00 1c 29 9f 1d
26 07 8d 00 1c 60 00 20 40 60 20 d8 05 b0 0b a9 00 20 57 06 ba 86 49 20 d1 f4 60 a9 03 85 71 a9
00 85 70 60 20 3b 07 4c 1e 04 00 67 63 41 61 c3 52 95 2d 52 8a 6d 94 a2 00 00 08 00 00 00 00 17
M-E at 0400, CRC 7021
* = 0400
0400 4C C4 04 JMP $04C4
0403 4C AA 04 JMP $04AA
0406 4C 65 05 JMP $0565
0409 4C 4D 05 JMP $054D
040C 4C 50 05 JMP $0550
040F 4C 5B 05 JMP $055B
0412 EA NOP
0413 EA NOP
0414 60 RTS
0415 EA NOP
0416 EA NOP
0417 60 RTS
0418 EA NOP
0419 EA NOP
041A 60 RTS
041B 4C 35 05 JMP $0535
041E 20 11 05 JSR $0511
0421 88 DEY
0422 B1 70 LDA ($70),Y
0424 AA TAX
0425 4A LSR A
0426 4A LSR A
0427 4A LSR A
0428 4A LSR A
0429 85 73 STA $73
042B 8A TXA
042C 29 0F AND #$0F
042E AA TAX
042F A9 00 LDA #$00
0431 8D 00 18 STA $1800
0434 A9 04 LDA #$04
0436 2C 00 18 BIT $1800
0439 F0 FB BEQ $0436
043B 8E 00 18 STX $1800
043E EA NOP
043F EA NOP
0440 8A TXA
0441 0A ASL A
0442 29 0F AND #$0F
0444 8D 00 18 STA $1800
0447 48 PHA
0448 68 PLA
0449 A5 73 LDA $73
044B 8D 00 18 STA $1800
044E EA NOP
044F EA NOP
0450 EA NOP
0451 0A ASL A
0452 29 0F AND #$0F
0454 8D 00 18 STA $1800
0457 98 TYA
0458 D0 C7 BNE $0421
045A 20 69 04 JSR $0469
045D A2 02 LDX #$02
045F 8E 00 18 STX $1800
0462 A9 04 LDA #$04
0464 2C 00 18 BIT $1800
0467 F0 FB BEQ $0464
0469 60 RTS
046A A0 00 LDY #$00
046C 20 11 05 JSR $0511
046F 88 DEY
0470 A9 04 LDA #$04
0472 2C 00 18 BIT $1800
0475 F0 FB BEQ $0472
0477 EA NOP
0478 EA NOP
0479 24 70 BIT $70
047B AD 00 18 LDA $1800
047E 0A ASL A
047F EA NOP
0480 24 70 BIT $70
0482 0D 00 18 ORA $1800
0485 EA NOP
0486 0A ASL A
0487 0A ASL A
0488 0A ASL A
0489 0A ASL A
048A 85 74 STA $74
048C AD 00 18 LDA $1800
048F 0A ASL A
0490 24 70 BIT $70
0492 48 PHA
0493 68 PLA
0494 0D 00 18 ORA $1800
0497 29 0F AND #$0F
0499 05 74 ORA $74
049B 91 70 STA ($70),Y
049D 98 TYA
049E D0 CF BNE $046F
04A0 A9 04 LDA #$04
04A2 2C 00 18 BIT $1800
04A5 F0 FB BEQ $04A2
04A7 4C 0B 05 JMP $050B
04AA 20 11 05 JSR $0511
04AD 68 PLA
04AE 68 PLA
04AF A0 00 LDY #$00
04B1 84 33 STY $33
04B3 A9 EC LDA #$EC
04B5 8D 0C 1C STA $1C0C
04B8 20 2C 05 JSR $052C
04BB 68 PLA
04BC 85 49 STA $49
04BE 38 SEC
04BF 66 3B ROR $3B
04C1 4C 4E 90 JMP $904E
04C4 AD 0F 18 LDA $180F
04C7 29 20 AND #$20
04C9 F0 06 BEQ $04D1
04CB 38 SEC
04CC 66 3B ROR $3B
04CE 20 32 90 JSR $9032
04D1 78 SEI
04D2 A5 49 LDA $49
04D4 48 PHA
04D5 A0 00 LDY #$00
04D7 88 DEY
04D8 D0 FD BNE $04D7
04DA 20 1A 05 JSR $051A
04DD F0 FB BEQ $04DA
04DF 20 0B 05 JSR $050B
04E2 20 1A 05 JSR $051A
04E5 F0 07 BEQ $04EE
04E7 20 2C 05 JSR $052C
04EA 58 CLI
04EB 20 05 05 JSR $0505
04EE 78 SEI
04EF A9 05 LDA #$05
04F1 85 71 STA $71
04F3 A9 21 LDA #$21
04F5 85 70 STA $70
04F7 A0 04 LDY #$04
04F9 20 6C 04 JSR $046C
04FC 20 25 05 JSR $0525
04FF 20 20 05 JSR $0520
0502 4C E2 04 JMP $04E2
0505 20 1A 05 JSR $051A
0508 D0 FB BNE $0505
050A 60 RTS
050B A9 02 LDA #$02
050D 8D 00 18 STA $1800
0510 60 RTS
0511 20 05 05 JSR $0505
0514 A9 00 LDA #$00
0516 8D 00 18 STA $1800
0519 60 RTS
051A A9 04 LDA #$04
051C 2C 00 18 BIT $1800
051F 60 RTS
0520 4C 00 10 JMP $1000
0523 00 BRK
0524 00 BRK
0525 AD 00 1C LDA $1C00
0528 09 08 ORA #$08
052A D0 05 BNE $0531
052C A9 F7 LDA #$F7
052E 2D 00 1C AND $1C00
0531 8D 00 1C STA $1C00
0534 60 RTS
0535 A9 00 LDA #$00
0537 85 22 STA $22
0539 20 2A 07 JSR $072A
053C A5 00 LDA $00
053E C9 02 CMP #$02
0540 B0 06 BCS $0548
0542 AD 03 03 LDA $0303
0545 29 80 AND #$80
0547 2C A9 03 BIT $03A9
054A 4C 5D 05 JMP $055D
054D A9 00 LDA #$00
054F 2C A9 02 BIT $02A9
0552 48 PHA
0553 20 2A 07 JSR $072A
0556 68 PLA
0557 A8 TAY
0558 20 44 07 JSR $0744
055B A5 00 LDA $00
055D 8D 00 03 STA $0300
0560 A0 01 LDY #$01
0562 4C 44 07 JMP $0744
0565 20 3B 07 JSR $073B
0568 20 6A 04 JSR $046A
056B 20 71 05 JSR $0571
056E 4C 5B 05 JMP $055B
0571 AD 00 1C LDA $1C00
0574 29 10 AND #$10
0576 D0 05 BNE $057D
0578 A9 08 LDA #$08
057A 85 00 STA $00
057C 60 RTS
057D 20 D8 05 JSR $05D8
0580 B0 FA BCS $057C
0582 A9 10 LDA #$10
0584 20 57 06 JSR $0657
0587 20 E9 F5 JSR $F5E9
058A 85 3A STA $3A
058C 20 8F F7 JSR $F78F
058F BA TSX
0590 86 49 STX $49
0592 20 10 F5 JSR $F510
0595 A2 08 LDX #$08
0597 50 FE BVC $0597
0599 B8 CLV
059A CA DEX
059B 10 FA BPL $0597
059D 8E 03 1C STX $1C03
05A0 A9 CE LDA #$CE
05A2 8D 0C 1C STA $1C0C
05A5 8A TXA
05A6 A2 05 LDX #$05
05A8 8D 01 1C STA $1C01
05AB B8 CLV
05AC 50 FE BVC $05AC
05AE B8 CLV
05AF CA DEX
05B0 D0 FA BNE $05AC
05B2 A0 BB LDY #$BB
05B4 B9 00 01 LDA $0100,Y
05B7 50 FE BVC $05B7
05B9 B8 CLV
05BA 8D 01 1C STA $1C01
05BD C8 INY
05BE D0 F4 BNE $05B4
05C0 B1 30 LDA ($30),Y
05C2 50 FE BVC $05C2
05C4 B8 CLV
05C5 8D 01 1C STA $1C01
05C8 C8 INY
05C9 D0 F5 BNE $05C0
05CB 50 FE BVC $05CB
05CD A9 EE LDA #$EE
05CF 8D 0C 1C STA $1C0C
05D2 8C 03 1C STY $1C03
05D5 84 50 STY $50
05D7 60 RTS
05D8 20 CF 06 JSR $06CF
05DB F0 29 BEQ $0606
05DD 20 A7 06 JSR $06A7
05E0 A5 22 LDA $22
05E2 38 SEC
05E3 ED 23 05 SBC $0523
05E6 F0 1B BEQ $0603
05E8 A2 FF LDX #$FF
05EA B0 06 BCS $05F2
05EC 49 FF EOR #$FF
05EE 69 01 ADC #$01
05F0 A2 01 LDX #$01
05F2 20 0D 06 JSR $060D
05F5 AD 23 05 LDA $0523
05F8 85 22 STA $22
05FA C9 24 CMP #$24
05FC 90 02 BCC $0600
05FE E9 23 SBC #$23
0600 20 15 07 JSR $0715
0603 A9 01 LDA #$01
0605 2C A9 03 BIT $03A9
0608 85 00 STA $00
060A C9 02 CMP #$02
060C 60 RTS
060D 0A ASL A
060E A8 TAY
060F 86 4A STX $4A
0611 AD 00 1C LDA $1C00
0614 29 FE AND #$FE
0616 85 70 STA $70
0618 A9 1E LDA #$1E
061A 85 71 STA $71
061C A5 70 LDA $70
061E 18 CLC
061F 65 4A ADC $4A
0621 45 70 EOR $70
0623 29 03 AND #$03
0625 45 70 EOR $70
0627 85 70 STA $70
0629 8D 00 1C STA $1C00
062C A5 71 LDA $71
062E 20 4E 06 JSR $064E
0631 A5 71 LDA $71
0633 C0 05 CPY #$05
0635 90 08 BCC $063F
0637 C9 11 CMP #$11
0639 90 0A BCC $0645
063B E9 02 SBC #$02
063D D0 06 BNE $0645
063F C9 1C CMP #$1C
0641 B0 02 BCS $0645
0643 69 04 ADC #$04
0645 85 71 STA $71
0647 88 DEY
0648 D0 D2 BNE $061C
064A 84 4A STY $4A
064C A9 4B LDA #$4B
064E 8D 05 18 STA $1805
0651 AD 05 18 LDA $1805
0654 D0 FB BNE $0651
0656 60 RTS
0657 85 45 STA $45
0659 A9 EE LDA #$EE
065B 8D 0C 1C STA $1C0C
065E A9 05 LDA #$05
0660 85 33 STA $33
0662 A9 23 LDA #$23
0664 85 32 STA $32
0666 A9 03 LDA #$03
0668 85 31 STA $31
066A A9 00 LDA #$00
066C 85 30 STA $30
066E A2 01 LDX #$01
0670 86 00 STX $00
0672 CA DEX
0673 8E AB 02 STX $02AB
0676 8E FE 02 STX $02FE
0679 86 3F STX $3F
067B 60 RTS
067C A0 00 LDY #$00
067E 84 3E STY $3E
0680 84 3D STY $3D
0682 88 DEY
0683 84 48 STY $48
0685 AD 00 1C LDA $1C00
0688 09 04 ORA #$04
068A 8D 00 1C STA $1C00
068D A9 20 LDA #$20
068F 24 20 BIT $20
0691 85 20 STA $20
0693 D0 E6 BNE $067B
0695 A2 01 LDX #$01
0697 8A TXA
0698 20 0D 06 JSR $060D
069B A2 FF LDX #$FF
069D A9 01 LDA #$01
069F 20 0D 06 JSR $060D
06A2 A9 FF LDA #$FF
06A4 4C 4E 06 JMP $064E
06A7 AD 23 05 LDA $0523
06AA C9 24 CMP #$24
06AC A5 22 LDA $22
06AE B0 09 BCS $06B9
06B0 C9 24 CMP #$24
06B2 90 0E BCC $06C2
06B4 E9 23 SBC #$23
06B6 18 CLC
06B7 90 07 BCC $06C0
06B9 C9 24 CMP #$24
06BB B0 03 BCS $06C0
06BD 69 23 ADC #$23
06BF 38 SEC
06C0 85 22 STA $22
06C2 AD 0F 18 LDA $180F
06C5 29 FB AND #$FB
06C7 90 02 BCC $06CB
06C9 09 84 ORA #$84
06CB 8D 0F 18 STA $180F
06CE 60 RTS
06CF 20 7C 06 JSR $067C
06D2 A5 1C LDA $1C
06D4 D0 09 BNE $06DF
06D6 A4 00 LDY $00
06D8 88 DEY
06D9 D0 04 BNE $06DF
06DB A5 22 LDA $22
06DD D0 35 BNE $0714
06DF 18 CLC
06E0 20 C2 06 JSR $06C2
06E3 20 95 06 JSR $0695
06E6 A9 04 LDA #$04
06E8 85 70 STA $70
06EA A9 30 LDA #$30
06EC 20 57 06 JSR $0657
06EF BA TSX
06F0 CA DEX
06F1 CA DEX
06F2 86 49 STX $49
06F4 20 B1 F3 JSR $F3B1
06F7 A5 18 LDA $18
06F9 85 22 STA $22
06FB A4 00 LDY $00
06FD 88 DEY
06FE F0 0C BEQ $070C
0700 C6 70 DEC $70
0702 30 0C BMI $0710
0704 A6 70 LDX $70
0706 20 1A 07 JSR $071A
0709 38 SEC
070A B0 DE BCS $06EA
070C 84 1C STY $1C
070E A8 TAY
070F 60 RTS
0710 A9 00 LDA #$00
0712 85 22 STA $22
0714 60 RTS
0715 20 4B F2 JSR $F24B
0718 85 43 STA $43
071A AD 00 1C LDA $1C00
071D 29 9F AND #$9F
071F 1D 26 07 ORA $0726,X
0722 8D 00 1C STA $1C00
0725 60 RTS
0726 00 BRK
0727 20 40 60 JSR $6040
072A 20 D8 05 JSR $05D8
072D B0 0B BCS $073A
072F A9 00 LDA #$00
0731 20 57 06 JSR $0657
0734 BA TSX
0735 86 49 STX $49
0737 20 D1 F4 JSR $F4D1
073A 60 RTS
073B A9 03 LDA #$03
073D 85 71 STA $71
073F A9 00 LDA #$00
0741 85 70 STA $70
0743 60 RTS
0744 20 3B 07 JSR $073B
0747 4C 1E 04 JMP $041E
1581 Disk Drive turboDisk[edit | edit source]
m-w: 0300 #20
4c fc 03 4c ea 03 4c d9 04 4c c1 04 4c c4 04 4c cf 04 ea ea 60 ea ea 60 ea ea 60 4c a6 04 1f 17
1d 15 1b 13 19 11 1e 16 1c 14 1a 12 18 10 00 08 02 0a 04 0c 06 0e 01 09 03 0b 05 0d 07 0f 00 80
20 a0 40 c0 60 e0 10 90 30 b0 50 d0 70 f0 20 48 04 88 84 fe b1 fc a8 29 0f aa a9 10 8d 01 40 a9
04 2c 01 40 f0 fb bd 1e 03 8d 01 40 ea ea ea 0a 29 0f 09 10 8d 01 40 98 4a 4a 4a 4a a8 ea b9 1e
03 8d 01 40 20 e9 03 0a 29 0f 09 10 8d 01 40 a4 fe d0 be 20 e9 03 20 4b 04 4c da 03 a0 00 20 48
04 84 fb 20 e9 03 a9 04 2c 01 40 f0 fb 20 e4 03 ad 01 40 0a 20 e7 03 0d 01 40 29 0f aa 20 e8 03
ad 01 40 0a 20 e7 03 0d 01 40 29 0f a8 bd 2e 03 19 3e 03 a4 fb 88 91 fc d0 c7 a9 04 2c 01 40 f0
fb 4c 42 04 ea ea ea ea ea 60 ad 7e 04 f0 03 20 72 04 20 7f 04 20 48 04 68 68 58 60 78 a9 00 8d
7e 04 a2 02 a0 00 88 d0 fd ca d0 fa 20 51 04 f0 fb 20 42 04 20 51 04 f0 0c 20 5c 04 b0 07 20 7f
04 58 20 3c 04 78 a9 04 85 fd a9 58 85 fc a0 04 20 9e 03 20 8c 04 20 57 04 4c 14 04 20 51 04 d0
fb 60 a9 12 8d 01 40 60 20 3c 04 a9 10 8d 01 40 60 a9 04 2c 01 40 60 4c 00 10 00 00 ad 7e 04 f0
1b a2 00 a0 00 20 51 04 d0 02 38 60 88 d0 f6 ca d0 f3 a2 04 20 6c ff a9 00 8d 7e 04 18 60 00 38
20 99 04 ad 00 40 29 bf 8d 00 40 60 38 20 99 04 ad 00 40 09 40 8d 00 40 18 ad 02 40 29 bf 90 02
09 40 8d 02 40 60 a5 25 f0 12 a9 b0 20 16 05 c9 02 b0 03 a9 00 2c a9 01 85 25 a9 03 85 06 4c cf
04 a9 00 2c a9 02 48 20 fd 04 68 a8 20 24 05 a5 06 8d 00 07 a0 01 4c 24 05 20 1b 05 20 9c 03 20
e5 04 4c cf 04 a9 00 8d fa 01 2c 01 40 70 08 a9 08 8d fa 01 85 06 60 a9 90 8d 7e 04 2c a9 80 ae
5a 04 86 13 ec 2a 05 f0 08 8e 2a 05 a2 00 8e 7e 04 ae 5b 04 86 14 a2 04 4c 54 ff a9 07 85 fd a9
00 85 fc 60 20 1b 05 4c 4e 03 00 a9 08 85 00 60 20 d8 05 b0 fa a9 10 20 57 06 20 e9 f5 85 3a 20
M-E at 0300, CRC 3dea
* = 0300
0300 4C FC 03 JMP $03FC
0303 4C EA 03 JMP $03EA
0306 4C D9 04 JMP $04D9
0309 4C C1 04 JMP $04C1
030C 4C C4 04 JMP $04C4
030F 4C CF 04 JMP $04CF
0312 EA NOP
0313 EA NOP
0314 60 RTS
0315 EA NOP
0316 EA NOP
0317 60 RTS
0318 EA NOP
0319 EA NOP
031A 60 RTS
031B 4C A6 04 JMP $04A6
031E .END
0340 20 A0 40 JSR $40A0
0343 C0 60 CPY #$60
0345 E0 10 CPX #$10
0347 90 30 BCC $0379
0349 B0 50 BCS $039B
034B D0 70 BNE $03BD
034D F0 20 BEQ $036F
034E 20 48 04 JSR $0448
0351 88 DEY
0352 84 FE STY $FE
0354 B1 FC LDA ($FC),Y
0356 A8 TAY
0357 29 0F AND #$0F
0359 AA TAX
035A A9 10 LDA #$10
035C 8D 01 40 STA $4001
035F A9 04 LDA #$04
0361 2C 01 40 BIT $4001
0364 F0 FB BEQ $0361
0366 BD 1E 03 LDA $031E,X
0369 8D 01 40 STA $4001
036C EA NOP
036D EA NOP
036E EA NOP
036F 0A ASL A
0370 29 0F AND #$0F
0372 09 10 ORA #$10
0374 8D 01 40 STA $4001
0377 98 TYA
0378 4A LSR A
0379 4A LSR A
037A 4A LSR A
037B 4A LSR A
037C A8 TAY
037D EA NOP
037E B9 1E 03 LDA $031E,Y
0381 8D 01 40 STA $4001
0384 20 E9 03 JSR $03E9
0387 0A ASL A
0388 29 0F AND #$0F
038A 09 10 ORA #$10
038C 8D 01 40 STA $4001
038F A4 FE LDY $FE
0391 D0 BE BNE $0351
0393 20 E9 03 JSR $03E9
0396 20 4B 04 JSR $044B
0399 4C DA 03 JMP $03DA
039C A0 00 LDY #$00
039E 20 48 04 JSR $0448
03A1 84 FB STY $FB
03A3 20 E9 03 JSR $03E9
03A6 A9 04 LDA #$04
03A8 2C 01 40 BIT $4001
03AB F0 FB BEQ $03A8
03AD 20 E4 03 JSR $03E4
03B0 AD 01 40 LDA $4001
03B3 0A ASL A
03B4 20 E7 03 JSR $03E7
03B7 0D 01 40 ORA $4001
03BA 29 0F AND #$0F
03BC AA TAX
03BD 20 E8 03 JSR $03E8
03C0 AD 01 40 LDA $4001
03C3 0A ASL A
03C4 20 E7 03 JSR $03E7
03C7 0D 01 40 ORA $4001
03CA 29 0F AND #$0F
03CC A8 TAY
03CD BD 2E 03 LDA $032E,X
03D0 19 3E 03 ORA $033E,Y
03D3 A4 FB LDY $FB
03D5 88 DEY
03D6 91 FC STA ($FC),Y
03D8 D0 C7 BNE $03A1
03DA A9 04 LDA #$04
03DC 2C 01 40 BIT $4001
03DF F0 FB BEQ $03DC
03E1 4C 42 04 JMP $0442
03E4 EA NOP
03E5 EA NOP
03E6 EA NOP
03E7 EA NOP
03E8 EA NOP
03E9 60 RTS
03EA AD 7E 04 LDA $047E
03ED F0 03 BEQ $03F2
03EF 20 72 04 JSR $0472
03F2 20 7F 04 JSR $047F
03F5 20 48 04 JSR $0448
03F8 68 PLA
03F9 68 PLA
03FA 58 CLI
03FB 60 RTS
03FC 78 SEI
03FD A9 00 LDA #$00
03FF 8D 7E 04 STA $047E
0402 A2 02 LDX #$02
0404 A0 00 LDY #$00
0406 88 DEY
0407 D0 FD BNE $0406
0409 CA DEX
040A D0 FA BNE $0406
040C 20 51 04 JSR $0451
040F F0 FB BEQ $040C
0411 20 42 04 JSR $0442
0414 20 51 04 JSR $0451
0417 F0 0C BEQ $0425
0419 20 5C 04 JSR $045C
041C B0 07 BCS $0425
041E 20 7F 04 JSR $047F
0421 58 CLI
0422 20 3C 04 JSR $043C
0425 78 SEI
0426 A9 04 LDA #$04
0428 85 FD STA $FD
042A A9 58 LDA #$58
042C 85 FC STA $FC
042E A0 04 LDY #$04
0430 20 9E 03 JSR $039E
0433 20 8C 04 JSR $048C
0436 20 57 04 JSR $0457
0439 4C 14 04 JMP $0414
043C 20 51 04 JSR $0451
043F D0 FB BNE $043C
0441 60 RTS
0442 A9 12 LDA #$12
0444 8D 01 40 STA $4001
0447 60 RTS
0448 20 3C 04 JSR $043C
044B A9 10 LDA #$10
044D 8D 01 40 STA $4001
0450 60 RTS
0451 A9 04 LDA #$04
0453 2C 01 40 BIT $4001
0456 60 RTS
0457 4C 00 10 JMP $1000
045A 00 BRK
045B 00 BRK
045C AD 7E 04 LDA $047E
045F F0 1B BEQ $047C
0461 A2 00 LDX #$00
0463 A0 00 LDY #$00
0465 20 51 04 JSR $0451
0468 D0 02 BNE $046C
046A 38 SEC
046B 60 RTS
046C 88 DEY
046D D0 F6 BNE $0465
046F CA DEX
0470 D0 F3 BNE $0465
0472 A2 04 LDX #$04
0474 20 6C FF JSR $FF6C
0477 A9 00 LDA #$00
0479 8D 7E 04 STA $047E
047C 18 CLC
047D 60 RTS
047E 00 BRK
047F 38 SEC
0480 20 99 04 JSR $0499
0483 AD 00 40 LDA $4000
0486 29 BF AND #$BF
0488 8D 00 40 STA $4000
048B 60 RTS
048C 38 SEC
048D 20 99 04 JSR $0499
0490 AD 00 40 LDA $4000
0493 09 40 ORA #$40
0495 8D 00 40 STA $4000
0498 18 CLC
0499 AD 02 40 LDA $4002
049C 29 BF AND #$BF
049E 90 02 BCC $04A2
04A0 09 40 ORA #$40
04A2 8D 02 40 STA $4002
04A5 60 RTS
04A6 A5 25 LDA $25
04A8 F0 12 BEQ $04BC
04AA A9 B0 LDA #$B0
04AC 20 16 05 JSR $0516
04AF C9 02 CMP #$02
04B1 B0 03 BCS $04B6
04B3 A9 00 LDA #$00
04B5 2C A9 01 BIT $01A9
04B8 85 25 STA $25
04BA A9 03 LDA #$03
04BC 85 06 STA $06
04BE 4C CF 04 JMP $04CF
04C1 A9 00 LDA #$00
04C3 2C A9 02 BIT $02A9
04C6 48 PHA
04C7 20 FD 04 JSR $04FD
04CA 68 PLA
04CB A8 TAY
04CC 20 24 05 JSR $0524
04CF A5 06 LDA $06
04D1 8D 00 07 STA $0700
04D4 A0 01 LDY #$01
04D6 4C 24 05 JMP $0524
04D9 20 1B 05 JSR $051B
04DC 20 9C 03 JSR $039C
04DF 20 E5 04 JSR $04E5
04E2 4C CF 04 JMP $04CF
04E5 A9 00 LDA #$00
04E7 8D FA 01 STA $01FA
04EA 2C 01 40 BIT $4001
04ED 70 08 BVS $04F7
04EF A9 08 LDA #$08
04F1 8D FA 01 STA $01FA
04F4 85 06 STA $06
04F6 60 RTS
04F7 A9 90 LDA #$90
04F9 8D 7E 04 STA $047E
04FC 2C A9 80 BIT $80A9
04FF AE 5A 04 LDX $045A
0502 86 13 STX $13
0504 EC 2A 05 CPX $052A
0507 F0 08 BEQ $0511
0509 8E 2A 05 STX $052A
050C A2 00 LDX #$00
050E 8E 7E 04 STX $047E
0511 AE 5B 04 LDX $045B
0514 86 14 STX $14
0516 A2 04 LDX #$04
0518 4C 54 FF JMP $FF54
051B A9 07 LDA #$07
051D 85 FD STA $FD
051F A9 00 LDA #$00
0521 85 FC STA $FC
0523 60 RTS
0524 20 1B 05 JSR $051B
0527 4C 4E 03 JMP $034E
052A 00 BRK
052B A9 08 LDA #$08
052D 85 00 STA $00
052F 60 RTS
0530 20 D8 05 JSR $05D8
0533 B0 FA BCS $052F
0535 A9 10 LDA #$10
0537 20 57 06 JSR $0657
053A 20 E9 F5 JSR $F5E9
053D 85 3A STA $3A
053F 20 00 00 JSR $0000
0542 .END
CMD HD Disk Drive turboDisk[edit | edit source]
m-w: 0500 #20
4c 54 06 4c 48 06 4c 0d 07 4c ed 06 4c f0 06 4c 03 07 ea ea 60 4c 41 07 ea ea 60 ea ea 60 00 1f
17 1d 15 1b 13 19 11 1e 16 1c 14 1a 12 18 10 00 08 02 0a 04 0c 06 0e 01 09 03 0b 05 0d 07 0f 00
80 20 a0 40 c0 60 e0 10 90 30 b0 50 d0 70 f0 2c 1e 05 30 4e 20 a4 06 88 84 fe b1 fc a8 29 0f aa
a9 10 8d 00 80 a9 04 2c 00 80 f0 fb bd 1f 05 8d 00 80 ea ea ea 0a 29 0f 09 10 8d 00 80 98 4a 4a
4a 4a a8 ea b9 1f 05 8d 00 80 20 47 06 0a 29 0f 09 10 8d 00 80 a4 fe d0 be 20 47 06 20 ac 06 4c
38 06 20 c8 05 88 b1 fc 2c 01 88 70 fb 8d 00 88 ad 02 88 09 80 8d 02 88 29 7f 2c 01 88 50 fb 8d
02 88 98 d0 e0 a2 92 2c a2 82 ad 02 88 8e 03 88 8d 02 88 60 2c 01 88 70 fb ae 00 88 ad 02 88 09
80 8d 02 88 29 7f 2c 01 88 50 fb 8d 02 88 8a 88 91 fc d0 e0 60 a0 00 2c 1e 05 30 d8 20 a4 06 84
fb 20 47 06 a9 04 2c 00 80 f0 fb 20 42 06 ad 00 80 0a 20 45 06 0d 00 80 29 0f aa 20 46 06 ad 00
80 0a 20 45 06 0d 00 80 29 0f a8 bd 2f 05 19 3f 05 a4 fb 88 91 fc d0 c7 a9 04 2c 00 80 f0 fb 4c
95 06 ea ea ea ea ea 60 20 a4 06 a5 49 29 bf 85 49 4c 30 ff 78 a2 02 a0 00 88 d0 fd ca d0 fa 20
bb 06 f0 fb 20 90 06 20 bb 06 f0 07 20 d1 06 58 20 8a 06 78 a9 06 85 fd a9 cd 85 fc a0 04 20 f7
05 20 de 06 20 cc 06 4c 67 06 20 bb 06 d0 fb 60 2c 1e 05 30 06 a9 12 8d 00 80 60 ad 02 88 29 7f
8d 02 88 60 20 8a 06 2c 1e 05 30 06 a9 10 8d 00 80 60 ad 02 88 09 80 8d 02 88 60 2c 1e 05 30 06
a9 04 2c 00 80 60 a9 40 2c 01 88 60 4c 00 10 00 00 a5 49 29 fe 85 49 ad 00 8f 09 01 d0 0b a5 49
09 41 85 49 a9 be 2d 00 8f 8d 00 8f 60 a9 00 2c a9 02 48 20 2e 07 68 a8 a5 69 85 fd a5 68 85 fc
20 4f 05 a5 20 8d 00 03 a0 01 4c 55 07 20 4c 07 20 f5 05 20 19 07 4c 03 07 a9 00 8d fa 01 2c 00
8f 30 08 a9 08 8d fa 01 85 20 60 a9 90 2c a9 aa ae cf 06 8e 00 28 ae d0 06 8e 01 28 a2 00 4c 4e
ff ad d6 2b 8d 00 03 a0 01 4c 55 07 a9 03 85 fd a9 00 85 fc 60 20 4c 07 4c 4f 05 1c b0 02 69 04
M-E at 0500, CRC 115
* = 0500
0500 4C 54 06 JMP $0654
0503 4C 48 06 JMP $0648
0506 4C 0D 07 JMP $070D
0509 4C ED 06 JMP $06ED
050C 4C F0 06 JMP $06F0
050F 4C 03 07 JMP $0703
0512 EA NOP
0513 EA NOP
0514 60 RTS
0515 4C 41 07 JMP $0741
0541 20 A0 40 JSR $40A0 // free ram
0544 C0 60 CPY #$60
0546 E0 10 CPX #$10
0548 90 30 BCC $057A
054A B0 50 BCS $059C
054C D0 70 BNE $05BE
054E F0 2C BEQ $057C
054F 2C 1E 05 BIT $051E
0552 30 4E BMI $05A2
0554 20 A4 06 JSR $06A4
0557 88 DEY
0558 84 FE STY $FE
055A B1 FC LDA ($FC),Y
055C A8 TAY
055D 29 0F AND #$0F
055F AA TAX
0560 A9 10 LDA #$10
0562 8D 00 80 STA $8000
0565 A9 04 LDA #$04
0567 2C 00 80 BIT $8000
056A F0 FB BEQ $0567
056C BD 1F 05 LDA $051F,X
056F 8D 00 80 STA $8000
0572 EA NOP
0573 EA NOP
0574 EA NOP
0575 0A ASL A
0576 29 0F AND #$0F
0578 09 10 ORA #$10
057A 8D 00 80 STA $8000
057D 98 TYA
057E 4A LSR A
057F 4A LSR A
0580 4A LSR A
0581 4A LSR A
0582 A8 TAY
0583 EA NOP
0584 B9 1F 05 LDA $051F,Y
0587 8D 00 80 STA $8000
058A 20 47 06 JSR $0647
058D 0A ASL A
058E 29 0F AND #$0F
0590 09 10 ORA #$10
0592 8D 00 80 STA $8000
0595 A4 FE LDY $FE
0597 D0 BE BNE $0557
0599 20 47 06 JSR $0647
059C 20 AC 06 JSR $06AC
059F 4C 38 06 JMP $0638
05A2 20 C8 05 JSR $05C8
05A5 88 DEY
05A6 B1 FC LDA ($FC),Y
05A8 2C 01 88 BIT $8801 // parallel io
05AB 70 FB BVS $05A8
05AD 8D 00 88 STA $8800 // parallel io
05B0 AD 02 88 LDA $8802 // parallel io
05B3 09 80 ORA #$80
05B5 8D 02 88 STA $8802 // parallel io
05B8 29 7F AND #$7F
05BA 2C 01 88 BIT $8801 // parallel io
05BD 50 FB BVC $05BA
05BF 8D 02 88 STA $8802 // parallel io
05C2 98 TYA
05C3 D0 E0 BNE $05A5
05C5 A2 92 LDX #$92
05C7 2C A2 82 BIT $82A2
05CA AD 02 88 LDA $8802 // parallel io
05CD 8E 03 88 STX $8803 // parallel io
05D0 8D 02 88 STA $8802 // parallel io
05D3 60 RTS
------------------------------------------- END
------------------------------------------- BEGIN
05D4 2C 01 88 BIT $8801 // parallel io
05D7 70 FB BVS $05D4
05D9 AE 00 88 LDX $8800 // parallel io
05DC AD 02 88 LDA $8802 // parallel io
05DF 09 80 ORA #$80
05E1 8D 02 88 STA $8802 // parallel io
05E4 29 7F AND #$7F
05E6 2C 01 88 BIT $8801 // parallel io
05E9 50 FB BVC $05E6
05EB 8D 02 88 STA $8802 // parallel io
05EE 8A TXA
05EF 88 DEY
05F0 91 FC STA ($FC),Y
05F2 D0 E0 BNE $05D4
05F4 60 RTS
------------------------------------------- END
------------------------------------------- BEGIN
05F5 A0 00 LDY #$00
05F7 2C 1E 05 BIT $051E
05FA 30 D8 BMI $05D4
05FC 20 A4 06 JSR $06A4
05FF 84 FB STY $FB
0601 20 47 06 JSR $0647
0604 A9 04 LDA #$04
0606 2C 00 80 BIT $8000 // serial io
0609 F0 FB BEQ $0606
060B 20 42 06 JSR $0642
060E AD 00 80 LDA $8000 // serial io
0611 0A ASL A
0612 20 45 06 JSR $0645
0615 0D 00 80 ORA $8000 // serial io
0618 29 0F AND #$0F
061A AA TAX
061B 20 46 06 JSR $0646
061E AD 00 80 LDA $8000 // serial io
0621 0A ASL A
0622 20 45 06 JSR $0645
0625 0D 00 80 ORA $8000 // serial io
0628 29 0F AND #$0F
062A A8 TAY
062B BD 2F 05 LDA $052F,X
062E 19 3F 05 ORA $053F,Y
0631 A4 FB LDY $FB
0633 88 DEY
0634 91 FC STA ($FC),Y
0636 D0 C7 BNE $05FF
0638 A9 04 LDA #$04
063A 2C 00 80 BIT $8000 // serial io
063D F0 FB BEQ $063A
063F 4C 95 06 JMP $0695
0642 EA NOP
0643 EA NOP
0644 EA NOP
0645 EA NOP
0646 EA NOP
0647 60 RTS
------------------------------------------- END
------------------------------------------- BEGIN
0648 20 A4 06 JSR $06A4
064B A5 49 LDA $49
064D 29 BF AND #$BF
064F 85 49 STA $49
0651 4C 30 FF JMP $FF30
------------------------------------------- END
------------------------------------------- first jump
0654 78 SEI
0655 A2 02 LDX #$02 //< a delay?! >
0657 A0 00 LDY #$00
0659 88 DEY
065A D0 FD BNE $0659
065C CA DEX
065D D0 FA BNE $0659 // >end of delay>
065F 20 BB 06 JSR $06BB
0662 F0 FB BEQ $065F
0664 20 90 06 JSR $0690
0667 20 BB 06 JSR $06BB
066A F0 07 BEQ $0673
066C 20 D1 06 JSR $06D1
066F 58 CLI // allow interrupts for a sec
0670 20 8A 06 JSR $068A
0673 78 SEI
0674 A9 06 LDA #$06
0676 85 FD STA $FD
0678 A9 CD LDA #$CD
067A 85 FC STA $FC // load address $06cd into $fd
067C A0 04 LDY #$04
067E 20 F7 05 JSR $05F7
0681 20 DE 06 JSR $06DE
0684 20 CC 06 JSR $06CC
0687 4C 67 06 JMP $0667
-------------------------------------------
068A 20 BB 06 JSR $06BB //
068D D0 FB BNE $068A
068F 60 RTS
------------------------------------------- END
-------------------------------------------
0690 2C 1E 05 BIT $051E // <-- from the delay
0693 30 06 BMI $069B
0695 A9 12 LDA #$12
0697 8D 00 80 STA $8000
069A 60 RTS // >back to the delay>
069B AD 02 88 LDA $8802 // parallel io
069E 29 7F AND #$7F
06A0 8D 02 88 STA $8802
06A3 60 RTS // and returning
------------------------------------------- END OF:
------------------------------------------- BEGIN
06A4 20 8A 06 JSR $068A
06A7 2C 1E 05 BIT $051E
06AA 30 06 BMI $06B2
06AC A9 10 LDA #$10
06AE 8D 00 80 STA $8000 // serial IO
06B1 60 RTS
06B2 AD 02 88 LDA $8802 // parallel IO
06B5 09 80 ORA #$80
06B7 8D 02 88 STA $8802 // parallel IO
06BA 60 RTS
------------------------------------------- END
-------------------------------------------
06BB 2C 1E 05 BIT $051E // <-- from the delay
06BE 30 06 BMI $06C6
06C0 A9 04 LDA #$04
06C2 2C 00 80 BIT $8000 // serial IO
06C5 60 RTS // >back to the delay>
06C6 A9 40 LDA #$40
06C8 2C 01 88 BIT $8801 // paralle IO
06CB 60 RTS
------------------------------------------- END
------------------------------------------- BEGIN
06CC 4C 00 10 JMP $1000
06CE 10 00 BPL $06D0
06CF 00 BRK
06D0 00 BRK
------------------------------------------- END
------------------------------------------- real work
06D1 A5 49 LDA $49 //
06D3 29 FE AND #$FE // make low bit of $49 0
06D5 85 49 STA $49 // for good
06D7 AD 00 8F LDA $8F00 // set low bit of LED IO byte
06DA 09 01 ORA #$01
06DC D0 0B BNE $06E9 // if $8f00 WAS not 0, save, rts
06DE A5 49 LDA $49 // if $8f00 WAS 0,
06E0 09 41 ORA #$41 // set lots of bits on $49
06E2 85 49 STA $49 // and save it
06E4 A9 BE LDA #$BE // and set lots of bits on LED IO byte
06E6 2D 00 8F AND $8F00 // by anding with the low bit LED IO byte
06E9 8D 00 8F STA $8F00 // and save it LED IO byte
06EC 60 RTS // > we are done >>>>>>>>>>>>>>>>>>>
------------------------------------------- done w/ real work
------------------------------------------- BEGIN
06ED A9 00 LDA #$00
06EF 2C A9 02 BIT $02A9
06F0 A9 02 LDA #$02
06F2 48 PHA
06F3 20 2E 07 JSR $072E
06F6 68 PLA
06F7 A8 TAY
06F8 A5 69 LDA $69 // store $6869 in $fc
06FA 85 FD STA $FD
06FC A5 68 LDA $68
06FE 85 FC STA $FC
0700 20 4F 05 JSR $054F
0703 A5 20 LDA $20
0705 8D 00 03 STA $0300
0708 A0 01 LDY #$01
070A 4C 55 07 JMP $0755
------------------------------------------- END
------------------------------------------- BEGIN
070D 20 4C 07 JSR $074C
0710 20 F5 05 JSR $05F5
0713 20 19 07 JSR $0719
0716 4C 03 07 JMP $0703
------------------------------------------- END
------------------------------------------- BEGIN
0719 A9 00 LDA #$00
071B 8D FA 01 STA $01FA // processor stack
071E 2C 00 8F BIT $8F00 // LED io
0721 30 08 BMI $072B
0723 A9 08 LDA #$08
0725 8D FA 01 STA $01FA // processor stack
0728 85 20 STA $20 // native mode job queue
072A 60 RTS
------------------------------------------- END
------------------------------------------- BEGIN
072B A9 90 LDA #$90
072E A9 AA LDA #$AA
0730 AE CF 06 LDX $06CF
0733 8E 00 28 STX $2800 // native mode job queue, tns vars
0736 AE D0 06 LDX $06D0
0739 8E 01 28 STX $2801 // native mode job queue, tns vars
073C A2 00 LDX #$00
073E 4C 4E FF JMP $FF4E // jump into the OS
------------------------------------------- END
------------------------------------------- BEGIN
0741 AD D6 2B LDA $2BD6 // DOS variables
0744 8D 00 03 STA $0300 // DOS Buffers
0747 A0 01 LDY #$01
0749 4C 55 07 JMP $0755
------------------------------------------- END
------------------------------------------- setting vector 0300 in $FC
074C A9 03 LDA #$03 // why are they doing this, what good is it?
074E 85 FD STA $FD
0750 A9 00 LDA #$00
0752 85 FC STA $FC
0754 60 RTS
------------------------------------------- END OF: setting vector 0300 in $FC
------------------------------------------- BEGIN
0755 20 4C 07 JSR $074C
0758 4C 4F 05 JMP $054F
------------------------------------------- END
