Fast serial bus protocol
Description of the protocol
See Serial Port for the physical and electrical description of the port.
The fast serial bus protocol uses the SRQ line for the clock, instead of CLK as the standard protocol uses. It shifts the bits using the shift register in the 6526 CIA chip. This usage was not possible in the VIC-20 or the 1541 disk drive, because the 6522 VIA chip had problems with its shift register that could cause received bits to be lost.
Detailed information on the fast protocol is hard to find. This article aims to fill that gap. Signals and timings described here are obtained by observing exchanges between a C128 and a 1571 drive, and from implementing the fast protocol on a Teensy 3.5 controller board; they describe a working implementation rather than minimum requirements.
The only known implementation of a fast controller is the C128. The 1571 and 1581 drives are fast peripherals; other third party peripherals may also implement the fast protocol.
How the controller requests the fast protocol
Immediately before it asserts ATN, the controller sends a $FF byte with the CLK line released. The CLK line distinguishes this request from data being sent with the fast protocol. Because the byte is $FF, the DATA line remains released; the only signal is eight short pulses on the SRQ line.
These eight pulses are not sent if a peripheral is currently listening, lest they be mistaken for a data byte.
The Commodore 128 sets the bit time to 10 microseconds. Hence the SRQ line pulses low for 5 μs, and high for 5 μs.
The controller then asserts ATN. Any bytes sent under ATN are sent using the standard serial protocol.
How the peripheral requests the fast protocol
If the peripheral has been requested to talk, no specific request is necessary. It can send bytes using the fast protocol as soon as ATN is released, provided of course that the controller requested it.
If the peripheral has been requested to listen, it must ask the controller to use the fast protocol. At the moment that the controller releases ATN, it is asserting CLK and the peripheral is asserting DATA. To request the fast protocol, the peripheral must wait for the controller to release CLK. It then sends a $00 byte, causing eight pulses on the SRQ line, and finally releases DATA. If the peripheral releases DATA first, the controller will use the standard protocol.
The 1571 drive sets the bit time to 7 microseconds. Hence the SRQ line pulses low for 3 μs, and high for 4 μs. It waits 45 μs after CLK is released before sending the first pulse on SRQ. It releases DATA 98 μs after the last SRQ pulse ends. These delays are simply how long the firmware takes to execute, and are not necessary; the burst can begin immediately after CLK is released, and the peripheral can release DATA as soon as the burst ends.
How to send a byte
The handshake between talker and listener proceeds as for the standard protocol. The talker may possibly signal EOI. The C128 reverts to the standard protocol for a byte on which it signals EOI, but it does not seem to require the peripheral to do so.
For the standard protocol, the first bit begins when the talker asserts CLK. For the fast protocol, the talker likewise asserts CLK, but it will keep CLK asserted until the byte is complete, rather than releasing it to signal a bit. The listener should be prepared to accept either the fast or the standard protocol at this point. It will clock in bits using the standard protocol if CLK is released first, and using the fast protocol if SRQ is asserted first.
While asserting CLK, the talker shifts out eight bits using the DATA line for the bits and the SRQ line for the clock. The listener shifts in each bit on the rising edge of SRQ. Note that the bits are shifted out in the opposite order from the standard protocol. That is, the standard protocol sends the least significant bit first, but the fast protocol sends the most significant bit first.
The byte ends on the eighth rising edge of SRQ. The listener acknowledges by asserting DATA. It then waits for the talker to release CLK. Finally, the listener releases DATA, and waits for the next CLK, which signals the start of the next byte.
The C128 sets the bit time to 10 microseconds, for SRQ low 5 μs and high 5 μs. The 1571 sets 7 μs, for SRQ low 3 μs and high 4 μs. A device that snoops the protocol can use this difference in timing to determine which device sent the byte.
This section is a work in progress.
The burst mode uses the same hardware as the fast serial protocol, but requires special commands to request and use, while the fast serial protocol is transparent to the application.