Reset refers to the process of returning the computer to the apparent default (or ground) state of the computer – with or without memory intact. The computer will return to the default start-up screen if the motherboard has not been damaged, modified or expanded.
 Hard Reset
Also known as a cold reset or cold start, the motherboard loses power during the reset and so the memory storage is lost. A hard reset generally occurs when the computer is turned-off. There is no reason to conduct a hard reset unless a soft reset cannot be performed, or devices are to be added to the user I/O ports and power must be eliminated before safe connection.
 Soft Reset
Also known as a warm reset or warm start, the motherboard does not lose power during the reset process and so the memory storage remains intact. A soft reset can be achieved through software or hardware. Using
UNNEW will re-enable any BASIC program listing residing in memory.
 Memory Addresses
The reset vector tells the CPU where to find the system reset routine. The address of this routine is stored in low byte then high byte order. For all MOS Technology 65XX CPUs, the system reset vector is stored at the same address. Table 1 shows the address details for some Commodore CPUs.
|Table 1 - Reset Vector and Reset Routine Addresses|
|CPU||Computer||Reset Vector Address||Reset Routine Address|
|MOS Technology 6502||PET 200x||$FFFC||65532||$FD38||64824|
|MOS Technology 6502||CBM 300x||$FFFC||65532||$FCD1||64721|
|MOS Technology 6502||PET 400x, CBM 800x, SuperPET 900x||$FFFC||65532||$FD16||64790|
|MOS Technology 6502||CBM 600/700||$FFFC||65532||$F997||63895|
|MOS Technology 6502B||VIC-20||$FFFC||65532||$FD22||64802|
|MOS Technology 6510||C64, SX-64||$FFFC||65532||$FCE2||64738|
|MOS Technology 7501||C16, C116, Plus/4||$E477||58487||$FF6F||65380|
|MOS Technology 8501||C16, C116, Plus/4||$8FFC||36860||$FF6F||65380|
|MOS Technology 8501||C128x||$FFF8||65528||$FF3D||65341|
 Method of Activation
 Software Activated
A reset can be achieved by using the commands JMP (machine code) followed by the hexadecimal address or SYS (BASIC) followed by the decimal address of the system reset routine. These commands will then activate the routine located at the address pointed to by the reset vector. For example, to reset the C64 from BASIC use
 Hardware Activated
Main article Reset Button
NMI and RES are triggered by an NE556 timer chip (NMI by timer A and RES by timer B) upon startup (the latter with a slight delay to ensure all ICs are supplied with proper voltages). As both the user I/O port and the serial port are directly linked to pin 40 of the CPU on 65xx, 75XX and 85XX CPUs, a reset button can be easily manufactured and fitted to activate the function from either port. There is also a RES on the cartridge expansion slot (pin C) which is utilised by many copying and editing cartridges such as Freeze Frame, Action Replay and Final Cartridge III.
 Example Code
 Commodore 64 Code
This is the default machine code routine to reset the C64:
; MOS 6510 System Reset routine ; Reset vector (Kernal address $FFFC) points here. ; ; If cartridge is detected then cartridge cold start routine is activated. ; If no cartridge is detected then I/O and memory are initialised and BASIC cold start routine is activated. FCE2 A2 FF LDX #$FF ; FCE4 78 SEI ; set interrupt disable FCE5 9A TXS ; transfer .X to stack FCE6 D8 CLD ; clear direction flag FCE7 20 02 FD JSR $FD02 ; check for cart FCEA D0 03 BNE $FCEF ; .Z=0? then no cart detected FCEC 6C 00 80 JMP ($8000) ; direct to cartridge cold start via vector FCEF 8E 16 D0 STX $D016 ; sets bit 5 (MCM) off, bit 3 (38 cols) off FCF2 20 A3 FD JSR $FDA3 ; initialise I/O FCF5 20 50 FD JSR $FD50 ; initialise memory FCF8 20 15 FD JSR $FD15 ; set I/O vectors ($0314..$0333) to kernal defaults FCFB 20 5B FF JSR $FF5B ; more initialising... mostly set system IRQ to correct value and start FCFE 58 CLI ; clear interrupt flag FCFF 6C 00 A0 JMP ($A000) ; direct to BASIC cold start via vector
 Post-Reset Cycles
|Table 2 - Reset Mechanics|
||When a 6502 is turned on, the stack pointer is initialized with zero. The BRK/IRQ/NMI/RES sequence pulls the instruction register (IR) to 0.|
||The first stack access happens at address $0100 – a push first stores the value at $0100 + SP, then decrements SP. In the BRK/IRQ/NMI case, this would have stored the high-byte of the PC. But for RES, it is a read cycle, not a write cycle, and the result is discarded.|
||SP is now 0xFF (even if the internal state does not reflect that), so the second stack access (which would have been the low-byte of PC) targets 0x01FF. Again, the result is discarded, and SP decremented.|
||SP is now 0xFE, and the third stack access, (the status register) happens at 0x01FE. SP is decremented again.|
||The internal state of the CPU now shows that SP is 0xFD, because it got decremented 3 times for the three fake push operations. The low-byte of the vector is read.|
||The high-byte of the vector is read.|
||The first actual instruction is fetched.|
Since the reset is not timing-critical, it does not matter whether a few cycles are wasted by completing the fake stack cycles.
 Reset Protection
Some programs have been known to incorporate reset protection by re-writing the kernal routine or reset vector. This process does not immobilise the reset, but prevents the user gaining access to the computer.